All modern computer processors use the concept of physical memory as well as virtual memory. While physical memory is static virtual memory is dynamic. They both work together to provide a robust memory management in the processor. Suppose, a task in the processor requires access to the memory, an instruction requests memory access.
The virtual memory address then translates the required memory to the physical memory address. This is accomplished with the help of a page table or TLB. In a computer there is a guest system which is usually the user end and a host system which is the processor end. When a virtual system is being run, the virtual memory on the host system works as the physical memory of the guest system. Thus the address translation is a vital aspect in all modern high end computer processors. Am efficient functioning of a processor demands an efficient memory translation.
Processor vendors therefore apply technologies called SLAT or Second Level Address Translation. With a multi-level page table, host page table can be viewed nested within the guest page table. SLAT works with Hyper V and is supported by both Intel and AMD processors. There is a definite algorithm for implementation of SLAT. For example, the number of levels required to be walked or hovered in order to find the translation, doubles when the guest-physical address is about the same size as the guest-virtual address. In this case, pages of same sizes are utilized.
The algorithms and processes of how the memory and pages are accessed can be changed in order to provide maximum efficiency. For example, sometimes, large pages are used in order to reduce the number of levels.
How SLAT works?
A processor has a Translation Lookaside Buffer (TLB) that participates in virtual to physical memory address translation. A TLB is a cache memory on the processor that stores all recently used page mappings. During an address translation process, the TLB first scans its cache to see if it already has the mapping info. If it finds a match, the equivalent physical address is provided. If the TLB doesn’t find any match, it gives a page error and then Windows checks the page table for the required mapping info. Now, if Windows finds a mapping, it simply writes it to the TLB, in order to initiate address translation. The data is then accessed. This buffer, thus minimizes the hypervisor overhead.
SLAT is called Extended Page Table (EPT) in Intel processors and Rapid Virtualization Indexing (RVI) in the AMD processors. It is supported on Nehalem architecture processors for Intel, and Barcelona processors and for AMD.